The present invention relates to a shift circuit used in an arithmetic control section in a data processing system.
There are two principal methods of shifting data: sequentially, bit by bit, or in units of several bits, in response to a synchronized signal such as a clock signal utilizing a shift register or a data multiplexer, and a method of shifting a desired amount of data in one clock signal or in one machine cycle using a multi-stage data multiplexer. Normally, the latter is adopted when a high-speed operation is required.
FIG. 1 shows a conventional shift circuit using a multi-stage multiplexer. The shift circuit in FIG. 1 performs a right or left shift operation of data X which has a 32-bit unit length in the range of 0 through 31 bits. Data having a 16-bit unit length may also be shifted in a circuit similar to that described above. A 32-bit data register 10 stores data X. A 32-bit data register 20 stores data Y which is shifted from the left or the right side thereof. If a logical shift operation is performed, Y=0 (all "0") is set, and if an arithmetic right shift operation is performed Y=S is set in the register 20. In this example, S denotes a sign of the data X.
A shifter 30 comprises data multiplexers 31, 32, 33 (hereinafter referred to as DMPX) which are connected in a multi-stage manner (in this example 3 stages). The shifter 30 has 32-bit inputs A, B and a 32-bit output C. The shifter 30 outputs 32-bit shifted data from the output C in accordance with the contents X of the register 10 which is input to the input A and the contents Y of the register 20 which is input to the input B. The DMPX 31 performs a shift operation in the left direction in units of 0, 16, 32 and 48 bits. The DMPX 32 performs a shift operation in the left direction in units of 0, 4, 8 and 12 bits. Further, the DMPX 33 performs a shift operation in the left direction in units of 0, 1, 2 and 3 bits. Now the construction of the DMPX will be described with reference to the DMPX 31 in FIG. 2.
The DMPX 31 has a function of selecting 4 positions of data (X.sub.0-15, X.sub.16-31, Y.sub.0-15, Y.sub.16-31) each of which is spaced apart by 16 bits so as to perform a left shift operation of 0, 16, 32 and 48 bits. The selection of the four positions is performed by the selecting switches S1 through S4 which are shown in FIG. 2. The linked data (64 bits) of the outputs from the selecting switches S1 through S4 is circularly shifted by 0, 16, 32 and 48 bits in one direction (the left direction) in accordance with the received data (64 bits) at the inputs A and B. In this case, the required number of bits to be input to the succeeding stage DMPX 32 will be 47 bits so that the switch S4 is unnecessary. Furthermore, the contents to be input to the switch S3 will be Y.sub.0-14, Y.sub.16-20, X.sub.0-14 and X.sub.16-30, of which the least significant bit is deleted from Y.sub.0-15, Y.sub.16-31, X.sub.0-15 and X.sub.16-31, respectively. The DMPX 32 selects 4 positions of data, each of which is spaced apart by 4 bits. The DMPX 32 performs a shift operation of 47 bit data supplied from the DMPX 31 in the left direction in any of the units of 0, 4, 8 and 12 bits to produce the upper 35 bit data to the DMPX 33. The DMPX 33 has a function of selecting 4 positions of data each of which is spaced apart by 1 bit. The DMPX 32 performs a shift operation of 35 bit data supplied from the DMPX 32 in the left direction in any of the units of 0, 1, 2 and 3 bits to produce 32 bit data to the output C.
The register 40 stores 6-bit shifting number data N which specifies the number of the shift in the left direction to the shifter 30. The lower 2 bits of the data N specify the four selecting positions of the DMPX 33. That is, the two bits "00", "01", "10" and "11" specify 0-bit, 1-bit, 2-bit and 3-bit shift-left operations, respectively. The two bits succeeding the lower two bits of the data N specify four positions of the DMPX 32. That is, the two bits "00", "01", "10" and "11" specify 0-bit, 4-bit, 8-bit and 12-bit shift-left operations, respectively. Further, the upper 2 bits of the data N specify 4 selecting positions of the DMPX 31. That is, the two bits "00", "01" "10" and "11" specify 0-bit, 16-bit, 32-bit and 48-bit shift-left operations, respectively. To perform a shift-left operation of the data X (X.sub.0-31) having a unit length of 32 bits by a desired number of bits m in the range of 0 through 31 bits (0.ltoreq.m.ltoreq.31), the desired number of shifts m may be set in the shifting number register 40. As described above, the shifter 30 has a function of circular-shifting in one direction (in the left direction). To perform a shift-right operation of m bits (0&lt;m.ltoreq.31), 2.sup.6 -m (=64-m) may be set in the shifting number register 40. That is, an arbitrary shift-left operation of 0 through 31 bits can be performed by setting the number N in the range of 0 through 31 (in binary notation "000000" through "011111" ) in the shift register 40. Similarly, an arbitrary shift-right operation of 1 through 31 bits can be performed by setting the number N in the range of 64-1 through 64-31 (in binary notation "111111" through "100001").
For example, to perform a shift-right operation of 5 bits, the N of 2.sup.6 -5=59 is set in the shifting number register 40 to cause the shifter 30 to perform the shift-left operation of 59 bits which is equivalent to the shift-right operation of 5 bits. That is, N=59 notates "111011" in binary form. The DMPX 31 through 33 perform shift-left operations of 48 bits, 8 bits and 3 bits, respectively, to produce data which is shifted by 59 bits in the left direction, that is, shifted by 5 bits in the right direction from the output C.
To construct a shift circuit of double word length data of 64 bits utilizing single word length data of 32 bits, the capacity of the registers 10 and 20 may be extended to twice the bit width of the registers in FIG. 1, that is to 64 bits. Further, the bit width of the inputs A, B and the output C may also be extended to 64 bits. The bit width of the shifting register 40 may also be extended from 6 bits to 7 bits.
However, this method of constructing a shift circuit for double word length data has the following drawbacks:
I. If such an extension is realized by utilizing two shift circuits in FIG. 1 which perform shift operations of single word length, complicated connections will result from the increased signal lines for connecting these two circuits. This can be seen from the construction of the DMPX 31 in FIG. 2. For example, to construct a DMPX which performs shift-left operations of 0 bit, 16 bits, 32 bits, 48 bits, 64 bits, 80 bits, 96 bits and 112 bits using two DMPX 31s, 1024 signal lines [8 (positions).times.16 (bits/position).times.(128/16)] are required to realize a selecting function of 8 positions which are spaced apart by 16 bits. This number of lines is extremely large compared to 256 lines [4 (positions).times.16 (bits/position).times.(64/16)] in the DMPX 31 in FIG. 2.
II. Even if an LSI (Large Scale Integrated) circuit including the double-word length shift circuit could be manufactured in theory, the actual mounting on the package would be difficult because of the increased number of I/0 pins.